1. Field of the Invention
The present invention relates to a memory device suitable for various memory accesses of multiple processors, and a memory system having the same.
2. Discussion of Related Art
With the developments of process and design technology, performance of an application processor (AP) which is a real system on chip (SoC) has been improved enough to replace a computer. A computer having a wired or wireless communication function has been developed using four or more processors, a hardware accelerator for multimedia and three dimensional (3D) data processing, and various peripheral devices. According to such an increase in operation performance of the SoC, as various functions are performed, a large amount of data is required. When a memory device cannot rapidly respond to data access requests, there is a problem in which entire system performance deteriorates.
A method of increasing a bandwidth of the memory device to solve the problem has been used until now. That is, a dynamic random access memory (DRAM) device mainly used as a main memory increases its bandwidth by increasing an instantaneous maximum transmission speed of an interface by increasing an operational frequency in a double data rate (DDRx) method.
Although, in the method, an instantaneous maximum bandwidth is increased in proportion to the operational frequency due to an operation method of the conventional DRAM devices, there is a problem in which an effective bandwidth is not increased as expected.
When one job is divided into several processes and the multiple processors simultaneously execute the processes, the processors can operate in a pipeline scheme by sequentially operating according to the order of accessing the memory device, and show successful performance. On the other hand, when the processors simultaneously perform different jobs, since there is a large possibility of accessing different address areas and characteristics and urgency of required data are different, performance of a specific operation deteriorates and also the entire system performance deteriorates when the memory cannot respond to the requests in time.
Meanwhile, in a system with multiple processors, a memory controller should respond and operate according to quality of service (QoS) types. One among methods to solve the problem uses a plurality of memory devices and makes the multiple processors access different memory devices. However, it is difficult for the method to apply since it increase manufacturing cost, a size of the system, and power consumption.